Photoresist developing track for silicon and quartz wafers
Key Features and Accessories:
Temperature controlled developer line. Wafer front- and backside rinsing with DIW. Two process chambers for developing. Wafer front- and backside rinsing with DIW. Two hot-plates at 110 C, one hot-plate at 22C temperature. Cassette to cassette wafer handling. Recipes: 1) development and bake 2) development only 3) bake only
AZ726 MIF developer in temperature controlled line. Hot-plate temperature 110 C.
Silicon and quartz wafers. IC-compatible metals.
Non-IC materials. Double side resist coated wafers not allowed due to likely particle contamination.
Availability and Cost: