Description:

Dual coat & develop photoresist processing track for silicon and quartz wafers.

Key Features and Accessories:

Three photoresist lines (SPR700, AZ5214E, AZ9235). EBR and backside wash capability. Temperature controlled developer line. Hot-plates with vacuum contact bake or proximity bake. Cassette to cassette wafer handling. About 50 wafers/hour can be coated or developed independently on the coat and develop lines. 

Key Specifications:

Positive photoresists: SPR700, AZ5214E, AZ9235. Thicknesses from 1.1 µm to 6.3 µm with single coating depending on the resist. AZ726 MIF developer. EBR solvent NBA.

Substrate Size:

150 mm

Allowed Materials:

Silicon and quartz wafers. IC-compatible metals.

Forbidden Materials:

Non-IC materials. Double side resist coated wafers not allowed due to likely particle contamination.

Availability and Cost:

Availability: F
Cost: Special